The present invention relates to a data receiving apparatus and a method of deinterleaving data for reproducing data transmitted by a modulation mode at a frame speed (or transmission rate) and by an interleaving mode arbitrarily selected from predetermined modulation modes, frame speeds and interleaving modes.
Hitherto, the NTT system and POCSAG system have been known as paging (wireless paging) systems.
The POCSAG system employs, for example, the binary FSK (Frequency Shift Keying) method as a modulation mode and sets a frame speed to 512 bps (Bit/Second). When paging is performed, a paging service company transmits digital data, which has been FSK-modulated, to the called pager, at the rated frame speed. Thus, a service for communicating messages has been performed.
Meanwhile, the progress of the mobile communication technique made recently has resulted in the communication service charge being reduced, thus resulting in an increase in subscribers. As a result, addresses for the subscribers are in short supply and the traffic is always congested. Thus, the conventional POCSAG system has encountered difficulty in providing satisfactory service for the subscribers.
Since the paging service has been in a great demand and the serviceable menus have been increased recently, there arise a necessity of improving the paging system. As a result, employment as "RCR STD-43" in the future has been decided as the next standard system.
The foregoing paging system (hereinafter called "STD-43") will briefly be described. The structure of data, which is employed in STD-43, is shown in FIG. 32. Referring to FIG. 32, symbol "A" shows the structure of data which is transmitted at a period of one hour and "B" shows one cycle of the data structure "A". Symbol "C" shows the structure of data in one frame of the cycle structure "B". Symbol "D" shows the block structure of one frame. The data structure "A" is composed of 15 cycles respectively given numbers "No. 0" to "No. 14".
The cycle structure "B" is composed of 128 frames respectively given numbers "No. 0" to "No. 127", which are transmitted at a period of four minutes. One frame has a data length of 1.875 seconds. Data in one frame of the frame structure cycle is sectioned into 8 sections corresponding to the contents of data.
The eight sections; of the data contents are as indicated in the data structure "C" and the block structure "D", composed of sync structure D1 composed of, when viewed from the leading end, synchronization 1 (S1)C1, frame information (F1) C2 and synchronization 2 (S2)C3 and arranged to be transmitted at 115 ms (milliseconds); and interleaved block structure D2 composed of block information (BI) C4, address field (AF)C5, vector field (VF)C6, message field (MF)C7 and idle blocks (IB)C8 and arranged to be transmitted at a frame speed of 160 ms for each block so that 11 blocks are transmitted.
In the synchronizing signal section D, the synchronization 1 (S1)C1 is composed of 112-bit 2-level FM data (binary-FSK-modulated data, in detail) at 1600 bps, the synchronization 1 (S1)C1 containing frame pattern data including information of frame receiving timing, timing for receiving 1600 bps symbol data and the transmitted type selected from the following four frame types/rates with which the interleaving block portion D1 is interleaved/transmitted:
1. 2-Level FM 1600 bps (Binary FSK Modulation/1600 bps) PA1 2. 2-Level FM 3200 bps (Binary FSK Modulation/3200 bps) PA1 3. 4-Level FM 3200 bps (Quadruple FSK Modulation/3200 bps) PA1 4. 4-Level FM 6400 bps (Quadruple FSK Modulation/6400 bps). PA1 1600 bps: any one of phases "a", "b", "c" and "d" is used (multiplex degree: 1) PA1 3200 bps: a pair of phases "a" and "c" or a pair of "b" and "d" is used (multiplex degree: 2) PA1 6400 bps: all of the phases "a", "b", "c" and "d" are used (multiplex degree: 4) PA1 Information (Information Bit): 21 bits PA1 Parity(Check Bit): 10 bits PA1 CK(Even-Number Parity Bit): 1 bit PA1 1600 bps: 1 phase.times.8 words.times.32 bits=256 bits PA1 3200 bps: 2 phases.times.8 words.times.32 bits=512 bits PA1 6400 bps: 4 phases.times.8 words.times.32 bits=1024 bits PA1 (1) A method in which plural types of hardware units (decoders) adaptable to the respective frame speeds and the multiplex degree are mounted on the pager; any one of the mounted hardware unit is selected so that data transmitted at any one of the frame speeds is received; and bit data of the interleaved block structure D2 of above data is reproduced in accordance with the multiplex degree and by the selected deinterleaving circuit. PA1 (2) One type of hardware is mounted on a pager; and software for performing control to rearrange bit data in the interleaved block structure D2 in accordance with the frame type of the received data is installed so that received data is reproducing. PA1 receiving means for receiving data; PA1 plural reproducing means capable of reproducing received data having a format which can be recognized by said data receiving apparatus; PA1 format data receiving means for receiving format data; and PA1 selection means for selecting one of said plural reproducing means in accordance with the format data received by said format data receiving means. PA1 receiving format data; and PA1 selecting one of said plural rearranging circuits in accordance with received format data.
The frame information (F1) C2 is composed of 32-bit 2-level FM data at 1600 bps and includes data (four bits) of cycle number of the cycle of the data structure "A" to which this frame belongs, data (7 bits) of the frame number of the cycle to which this frame belongs, and information of indication of plural transmitted operations and the number of the transmitted operations.
The interleaved block structure D2 formed of the synchronization 2 (S2)C3 and the block information (B1) C4 to the idle blocks (IB)C8 is data which is transmitted by means of the frame type specified by the synchronization 1 (S1)C1. The synchronization 2 (S2)C3 is a block for supplying timing information to the interleaved block structure D2 transmitted by the modulation method and the frame speed specified by the synchronization 1 (S1)C1 to enable the called pager to fetch the interleaved block structure D2.
The block information (BI)C4 is data disposed in block #0 of the interleaved block structure D2 and composed of one word. The block information (BI)C4 includes block information 1 for storing information of the word number (2 bits) which is used as the start point of address field (AF)C5 and the end point of the present field, to be described later, the word (6 bits) which is used as the start point of vector field (VF)C6 and the like, and block information items 2, 3 and 4 so that ID of the simulcast system and, if the frame number is zero, information of the actual time, time zone and system message are stored.
The address field (AF)C5 is a field for storing address data of the called pager, the data to be stored being short address (32 bits) or long address (64 bits).
The vector filed (VF)C6 and the address field (AF)C5 form a pair and the vector field (VF)C6 is a field for storing the word at which the own message data is started in a message field (MF)C7 to be described later, the word length of own message data (hereinafter simply referred to message length) and information of the data format of the own message data.
The message field (MF)C7 is a field for storing message data corresponding to information specified by the vector field (VF)C6. The idle blocks (IB)C8 is an unused block to which a pattern composed of "1" or "0" is set.
The signal format shown in FIG. 32 is, in parallel, interleaved/transmitted in a time sequential manner in independent four phases "a", "b", "c" and "d". That is, if STD-43 is employed, the paging service company uses any one of the above-mentioned four phases or two to four phases to enable data in one frame having different contents to be multiplexed so as to be transmitted simultaneously.
In STD-43, the relationship between the phases of the frame speeds is regulated as follows:
The block structure of the interleaved block structure D2 will now be described. Referring to FIG. 32, one block is structured such that the frame speed is 160 ms. One block stores, in parallel, 8 rows (one row is called one word) for one phase, each row being composed of the following 32 bits:
The number of bits of data in one block is different depending upon the frame speed. The relationship between the frame speeds and the number of bits of data in one block is as follows:
The structure of bit data in one block at each frame speed will now be described with reference to FIG. 33 to 35. FIG. 33 shows the structure of bit data in one block at the frame speed of 1600 bps, FIG. 34 shows the structure of bit data in one block at the frame speed of 3200 bps and FIG. 35 shows the structure of bit data in one block at the frame speed of 6400 bps.
In the case where the interleaved block structure D2 is transmitted at 1600 bps, the structure of bit data in one block shown in FIG. 33 is employed. The transmitted order of bit data is, in a direction indicated by an arrow .beta. shown in FIG. 33, as W(word)0a1, W1a1, W2a1, . . . , W5a32, W6a32 and W7a32.
In the case where transmitted at 3200 bps is performed, the structure of bit data in one block as shown in FIG. 34 is employed. The transmitted order of bit data is, in a direction indicated by an arrow .beta. shown in FIG. 34, as W0a1, W0c1, W1a1, . . . , W6c32, W7a32 and W7c32 (in the case of 2-level FM), as W0a1 and W0c1, W1a1 and W1c1, W2a1 and W2c1, . . . , W6a32 and W6c32, W7a32 and W7c32 (in the case of 4-level FM). In the case where transmitted at 6400 bps is performed, the structure of bit data in one block as shown in FIG. 35 is employed. The transmitted order of bit data is, in a direction indicated by an arrow .beta. shown in FIG. 35, as W0a1 and W0b1, W0c1 and W0d1, W1a1 and W1b1, W1c1 and W1d1, . . . , W6a32 and W6b32, W6c32 and W6d32, W7a32 and W7b32, W7c32 and W7d32 (in the case of 4-level FM).
As described above, STD-43 involves the number of bits of data in one block which is received at each frame speed and the interleaving mode being different. Also in the case of the frame speed of 3200 bps, the structure of bit data becomes different depending upon whether the modulation mode is 2-level FM or 4-level FM.
When a paging service company employs paging system STD-43, one frame type is selected from four types of the frame types/rates in the synchronization 1 (S1)C1 of the sync structure D1. Thus, the number of bits of data in one frame which is transmitted to the called pager can arbitrarily be changed.
Therefore, if the called pager uniformly receives, amplifies and digitizes data, which has been transmitted in the wireless manner, to simply convert 2-level FM serial data into parallel data as has been performed by the conventional POCSAG system, meaningless serial data is unintentionally transmitted. Thus, a data reproducing method adaptable to STD-43 and capable of rearranging bit data to correspond to the received frame type must be provided for the pager.
The following methods of reproducing received data to be provided for the pager have been suggested:
In the case where method (1) is employed, the pager is provided with a plurality of S/P conversion circuits for converting the serial data to the parallel data in accordance with the frame type of received data; and a rearranging circuit for rearranging the parallel data in order to separate data into each phase. In the case where method (2) is employed, one S/P conversion circuit and the rearranging circuit are provided which are controlled by software. However, in the above-mentioned case (1), the number of hardware units which receive and reproduce data and which must be provided for the pager increases. What is even worse, since the structure of each of the circuits has a complicated structure, the size of the reception processing circuit after it has been mounted cannot be reduced. In the case of (2), the software must perform a heavier task and therefore the structure of the system becomes too complicated.